Methods and apparatus to remove epitaxial defects in semiconductors

ABSTRACT

Methods and apparatus to remove epitaxial defects in semiconductors are disclosed. A disclosed example multilayered die structure includes a fin having a first material, where the fin is epitaxially grown from a first substrate layer having a second material, and where a defect portion of the fin is etched or polished. The disclosed example multilayered die structure also includes a second substrate layer having an opening through which the fin extends.

FIELD OF THE DISCLOSURE

This disclosure relates generally to semiconductor fabrication, and,more particularly, to methods and apparatus to remove epitaxial defectsin semiconductors.

BACKGROUND

In recent years, semiconductor devices such as microprocessors (e.g.,processors) have become smaller and more compact while their dietransistor counts have increased dramatically due to increasingcomputational needs (e.g., transistor counts in the billions). Toincrease compactness and/or functionality, some semiconductor structuresmay incorporate semiconductor regions formed of epitaxially-depositedmaterials (e.g., a semiconductor layer deposited and/or grown), whichcan differ in composition from a semiconductor substrate that is appliedwith the epitaxially-deposited materials. In turn, this difference incomposition can lead to defects resulting from mismatched molecularlattices at an interface between the semiconductor substrate and theepitaxially-deposited materials.

In a particular example, a defect region/portion resulting frommismatched molecular lattices (e.g., a material mismatch) may existwhere a fin structure having a first material extends from asemiconductor substrate having a second material. In such examples, thefin structure may be epitaxially grown from the base semiconductorstructure (e.g., deposited atoms onto the base structure) such thatmolecular lattice structures of the first material are mismatched withthe second material. The resultant defect region of the fin and/or thesubstrate can cause loss of strength and/or functionality and enabledeleterious electrical leakage current (e.g., electrical functionality).

In some examples, defect regions are simply left within semiconductordevices. However, these defect regions may manifest as early componentfailures caught during screening, thereby reducing device yields, orlatent defects, which may cause reliability issues during operation.Further, the aforementioned defect regions may result in leakage currentand/or necessitate the use of higher power for operation of functioningdevices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 A illustrates an example wafer in which the examples disclosedherein may be implemented.

FIG. 1B illustrates an example die that may be cut from the wafer ofFIG. 1A.

FIGS. 2A-2D are detailed cross-sectional views of an example layeredstructure of the example wafer of FIG. 1A, in which the examplesdisclosed herein may be implemented.

FIG. 2E shows photographs of cross-sections that indicate epitaxialgrowth/deposition mismatch of a semiconductor device.

FIGS. 3A-3C are cross-sectional views of the example layered structureshown in FIGS. 2A-2D, illustrating an example method in accordance withthe teachings of this disclosure.

FIGS. 4 and 5 are cross-sectional views illustrating an example backfilling process that may be implemented in the examples disclosedherein.

FIG. 6 is a cross-sectional view illustrating an example polishingprocess that may be implemented in the examples disclosed herein.

FIG. 7 is a cross-sectional view illustrating an example semiconductorlayering process in accordance with the teachings of this disclosure.

FIG. 8 depicts an example trapezoidal fin structure that may be definedusing the examples disclosed herein.

FIG. 9 depicts an example device structure that may be defined using theexamples disclosed herein.

FIG. 10 depicts yet another example device structure that may be definedusing the examples disclosed herein.

FIG. 11 is flowchart representative of an example method that may beused to implement the examples disclosed herein.

FIG. 12 is flowchart representative of another example method that maybe used to implement the examples disclosed herein.

FIG. 13 is a processor platform that may be used to execute the examplemethods disclosed herein.

The figures are not to scale. Instead, to clarify multiple layers andregions, the thickness of the layers may be enlarged in the drawings.Wherever possible, the same reference numbers will be used throughoutthe drawing(s) and accompanying written description to refer to the sameor like parts. As used in this patent, stating that any part (e.g., alayer, film, area, or plate) is in any way positioned on (e.g.,positioned on, located on, disposed on, or formed on, etc.) anotherpart, means that the referenced part is either in contact with the otherpart, or that the referenced part is above the other part with one ormore intermediate part(s) located therebetween. Stating that any part isin contact with another part means that there is no intermediate partbetween the two parts.

DETAILED DESCRIPTION

Methods and apparatus to remove semiconductor epitaxial defects aredisclosed. As a result of integrating different substrate materials insemiconductor fabrication, for example, defects due to mismatchedmolecular lattices of the materials can manifest. In particular, asemiconductor layer may be deposited and/or grown onto a basesemiconductor substrate. For example, a defect region may exist where afin structure of a first material extends from a semiconductor substrateof a second material. In such examples, the fin structure may beepitaxially grown from the base semiconductor structure such thatmolecular lattice structures of the first material are mismatched withthose of the second material. These mismatched molecular structures can,thus, define a defect region which, in turn, can result in a potentialloss of strength and/or functionality.

In some known examples, defect regions are simply left within (e.g.,left embedded within) semiconductor devices. For example, a defectregion may be embedded within a manufactured layered die structure cutfrom a wafer. However, these defect regions may manifest as immediatecomponent failures or latent defects. Further, the defect regions mayresult in leakage current and can prevent integration of differentsemiconductor materials such as Silicon along with Silicon-Germanium.Even further, the defect regions may result in higher powerconsumption/needs for their respective devices.

The examples disclosed herein remove and/or reduce these defect regionsthat result from integration/application of different semiconductormaterials, which can result in molecular lattice misalignment ofinterfacing atoms (e.g., misalignment caused by epitaxialgrowth/deposition). As a result, the examples disclosed herein enablereduction of potential leakage current and also enable use of materialand/or material systems that are typically difficult to integrate withSilicon, such as Silicon-Germanium (SiGe), Germanium, Germanium Tin,Indium Gallium Arsenide (InGaAs) and/or Group III-V compoundsemiconductors, etc. The examples disclosed herein also enable areduction in power consumption of semiconductor devices.

To remove defect regions (e.g., areas and/or volumes of molecularmisalignment from epitaxial growth), the examples disclosed utilize aremoval process to expose a portion of a substrate fin, which isepitaxially grown from a substrate of a different material, andselectively etch and/or polish a portion of the substrate fin that has adefect region. In some examples, the substrate and/or the fin areannealed after the portion is etched. Additionally or alternatively, insome examples, an opening defined by the etching process is back filled(e.g., back filled with a lattice compatible or compliant gap fillermaterial such as a flowable oxide or other similar material). Theexamples disclosed herein also enable angled contours and/or fin shapessuch as trapezoids and/or inclined surfaces. The examples disclosedherein also enable integration of wiring and/or devices within finstructures and/or fin shapes.

FIG. 1A illustrates an example wafer 100 in which the examples disclosedherein may be implemented. The wafer 100 of the illustrated exampleconsists of multiple semiconductor dies. In this example, the individualsemiconductor dies are functionally tested prior to being separated(e.g., cut) from the wafer 100. In particular, test patterns areprovided to each individual die and each individual die is monitored tohave a designated response. In some examples, faulty dies discoveredduring this testing are discarded.

FIG. 1B illustrates an example die (e.g., a microprocessor die) 102 thatmay be cut from the wafer 100 of FIG. 1A. In this example, the die 102is cut from the wafer 100 and separated (e.g., cut and/or sliced) fromthe wafer 100 after being successfully tested with the aforementionedfunctionality test described above. The die 102 of the illustratedexample may be used for a microprocessor or any other semiconductordevice, for example.

FIGS. 2A-2D are detailed cross-sectional views of an example layeredstructure 200 of the example wafer 100 of FIG. 1A, in which the examplesdisclosed herein may be implemented. The example of FIGS. 2A-2Drepresents a typical process that can result in an epitaxialregrowth/damage portion that, in turn, can result in leakage current,which potentially reduces performance (e.g., computational performance)of a corresponding semiconductor device. Turning to FIG. 2A, a substrate(e.g., an interlayer dielectric) 202, which is Silicon in this example,is shown having a fin 203 extending into another substrate (e.g., atrench gap fill) 204. In particular, the fin 203 of the illustratedexample represents a single fin of a fin pattern of the substrate 202.

FIG. 2B depicts the layered structure 200 after the fin 203 has beenetched. In this example, the etching process has defined a cavity 210 inthe substrate 204 that extends to the substrate 202. According to theillustrated example, the cavity 210 is formed by selectively etching thefin 203 shown in FIG. 2A. Additionally or alternatively, the fin 203 isetched via a timed etching process that controls a penetration depthand/or penetration area.

Turning to FIG. 2C, an epitaxial regrowth process is shown. Inparticular, a fin 206 is epitaxially grown in the cavity 210 shown inFIG. 2B. The fin 206 of the illustrated example is defined by depositingapplying atoms/material into the cavity 210. However, the fin 206 iscomposed of a different material (e.g., Germanium) than the substrate202. As a result of this material mismatch (e.g., a difference inmolecular structures/arrangement), a defect region (e.g., a defectportion, a defect volume, a defect area, etc.) 211 is present at orproximate an interface between the substrate 202 and the fin 206. Thisdefect region 211 defines a portion/volume in which interfacingmolecular structures of different materials have lattice mismatches.Thus, the defect region 211 may result in component defects (e.g.,leakage currents, etc.) and/or lack of internal structural integrity ofinterconnections and/or components. The extent of the effect(s) of thedefect region 211 may be dependent on the degree of molecular latticemisalignment between a first material of the substrate 202 and a secondmaterial of the fin 206. In this example, a side 212 is designated as aback side of the wafer 100.

FIG. 2D illustrates further processing of the layered structure 200. Ascan be seen in the illustrated view of FIG. 2D, a gate (e.g., asemiconductor gate) 216 has been defined on, over and/or surrounding thefin 206. As a result of this further processing (e.g., front sideprocessing), the defect region 211 is still present at an interface ofthe fin 206 and the substrate 202. As explained above, this defectregion 211 may impair and/or negatively affect operation of thissemiconductor device.

FIG. 2E shows photographs of cross-sections of a semiconductor devicethat indicate epitaxial growth/deposition mismatch. As can be seen inthe illustrated example, epitaxially grown fins 218 extend from asubstrate 220. Additionally, below a line 222, defect regions 224corresponding to each of the fins 218 are shown.

FIGS. 3A-3C are cross-sectional views of the example layered structure200 shown in FIGS. 2A-2D, illustrating an example method in accordancewith the teachings of this disclosure. Turning to FIG. 3A, the layeredstructure 200 is shown inverted (e.g., upside down) from the views shownin FIGS. 2A-2D to illustrate processing on the back side 212 of thesubstrate 202. According to the illustrated example, the gate 216described above has been applied with a substrate 302.

Turning to FIG. 3B, a portion of the substrate 202 is removed to definean exposed surface 304 of the substrate 206. In particular, thesubstrate 202 has been etched to expose the defect region 211 of the fin206. The etching process may be mechanical, chemical and/orphotochemical. While an etching process is described in this example,additionally or alternatively, a polishing process may be used to exposethe defect region 211. Alternatively, a polishing and/or etching processmay be used to define an opening (e.g., an annular opening) and/orcavity in/on the substrate 202 that is proximate the defect region 211so that the defect region 211 can be exposed for etching, for example.

FIG. 3C illustrates the layered structure 200 after the defect region211 has been removed, thereby defining an opening 310. In this example,the opening 310 exposes a portion of the fin 206 that does not include asignificant amount of defects (e.g., does not include any portion of thedefect region 211). In some examples, the layered structure 200 isfurther processed such that the opening 310 is still present as a cavity(e.g., a pocket) after further layering and/or structures (e.g.,interconnects, components) are added above the substrate 204 (in theview of FIG. 3C).

In some examples, an annealing process may be implemented in theexamples disclosed herein. In some examples, after the defect region 211has been etched (as described above in connection with FIG. 3C), anannealing process is applied. In such examples, heat, which is generallyindicated by lines 314, is applied to the layered structure 200 in a lowtemperature annealing process, for example, and the layered structure200 is later slowly cooled after being heated. According to theillustrated example, the annealing process is used to removeetch-related interfacial charge and/or defects (e.g., defects associatedwith the etching process).

In some other examples, the layered structure 200 is annealed in a hightemperature process. Additionally or alternatively, a Hydrogen annealingprocess utilized. In particular, deuterium (H₂) may be applied at a hightemperature (e.g., 450° C. (degrees Celsius)) and/or at a relativelyhigh pressure (e.g., 12 atmosphere (atm)). While annealing conditions,temperatures and pressures are described above, any appropriateconditions and/or annealing techniques may be used that are appropriateto an application, thickness, desired component spacing and/or structure(e.g., a desired layered arrangement), etc.

FIGS. 4 and 5 are cross-sectional views illustrating an example backfilling process that may be implemented in the examples disclosedherein. In some examples, exposed portions of fins 206 are coveredand/or back filled after an etching and/or polishing process. Turning tothe illustrated example of FIG. 4, the opening 310 of the layeredstructure 200 is filled (e.g., back filled) with material to prevent acavity and/or pocket from being formed above the fin 206. As a result, aback fill (e.g., a back fill material) 402 is deposited in the opening310. In this example, an end 404 of the back fill 402 is in relativelyclose alignment with the exposed surface 304 of the substrate 206.However, in other examples, the end 404 may extend past the exposedsurface 304 or be recessed below the exposed surface 304.

Turning to FIG. 5, an alternative exemplary application of back fillmaterial to FIG. 4 is shown in FIG. 5. According to the illustratedexample, a back fill 502 is applied to the layered structure 200 to fillthe opening 310 as well as extend beyond the exposed surface 304 (incontrast to the example of FIG. 4), thereby defining a layer (e.g., abarrier, a protective layer, etc.) 504 of the layered structure 200.

The back fill 402 and/or the back fill 502 shown in FIGS. 4 and 5,respectively, may be an insulating dielectric (e.g., a non-conductiveback filler material). Alternatively, the back fill 402 and/or the backfill 502 may include a conductive material and/or dielectric. In someexamples, metallization may occur after application of the back fillmaterial (e.g., above the back fill 502 in the view of FIG. 5).

FIG. 6 is a cross-sectional view illustrating an example polishingprocess that may be implemented in the examples disclosed herein. Inparticular, this polishing process may be implemented after the step ofFIG. 3B. Additionally or alternatively, the polishing process shown maybe implemented in conjunction with any of the processes described abovein connection with FIGS. 4 and 5, for example. As seen in theillustrated example, a polishing process (e.g., a mechanical polishingprocess) may be used to remove the defect region 211 and/or a portion ofthe defect region 211, thereby exposing a surface 602. In some examples,further layers may be added and/or metallization may be defined on thesurface 602.

FIG. 7 is a cross-sectional view illustrating an example semiconductorlayering process in accordance with the teachings of this disclosure. Inthis example, a layered structure 700 is shown that includes a substrate702, a defect region 704 and an applied/deposited substrate (e.g., asemiconductor substrate layer) 706 above the defect region 704. In thisexample, additional layers and/or metallization may be provided (e.g.,deposited) above (as viewed in FIG. 7), within and/or on the examplesubstrate 706. In this example, the substrate 702 along with at least aportion of the defect region 704 are then removed by an etching processand/or a polishing process, as indicated by a removed portion 708 of thelayered structure 700. The example process of FIG. 7 may be appliedacross a partial section of a die. In other words, the portions of thesubstrate 702 along with portions of the defect region 704 may beremoved by polishing and/or etching a pattern (e.g., defined by a resistlayer).

FIG. 8 depicts an example trapezoidal fin structure 800 that may bedefined using the examples disclosed herein to remove epitaxial defects.According to the illustrated example, the fin structure 800 includestrapezoidal fins 802 that extend from a substrate base 804, which may bea substrate layer similar to the substrate 204 or may be a back filledlayer such as the back fill layer 504. In this example, each of thetrapezoidal fins 802 include a ramped surface 806 as well as convergingtip 808 that defines a relatively flat surface in this example.

FIG. 9 depicts an example device structure 900 that may be defined usingthe examples disclosed herein. In this example, the device structure 900includes a substrate base 902, a back fill material layer 903, a fin 904that extends from the substrate base 902, as well as a device (e.g., atransistor, a gate, a diode, etc.) 906. The fin 904 of the illustratedexample also includes interconnects (e.g., metallized interconnects,wires) 910 that are electrically isolated from one another and extendfrom and/or through different portions of the fin 904 along an upwarddirection (as viewed in FIG. 9).

In some examples, the fin 904 has a trapezoidal shape and/orinclined/ramped surfaces. However, in other examples, any appropriategeometry and/or shape may be defined.

FIG. 10 depicts yet another example device structure 1000 that may bedefined using the examples disclosed herein. According to theillustrated example, the device structure 1000 includes a fin 1002extending from a substrate 1003 as well as transverse wires 1004extending therethrough. The transverse wires (e.g., nanowires) 1004 ofthe illustrated example may be used to electrically couple one or morecomponents (e.g., transistors, diodes, etc.) of a semiconductor waferand/or die. While the example structures disclosed herein include fins,trapezoidal components, device structures, support structures and/orwire structures, the examples disclosed herein may be used to define anyother appropriate semiconductor structure.

FIG. 11 is flowchart representative of an example method 1100 that maybe used to implement the examples disclosed herein. In this example, afin (e.g., the fin 206) is to be processed to remove a defectportion/region (e.g., the defect portion 211). In this example, the finhas been epitaxially grown from a substrate and has a different materialfrom the substrate.

A portion of a substrate (e.g., the substrate 202, the substrate 702) isremoved to expose the fin (e.g., the fin 206) (block 1102). The portionmay be removed via an etching and/or polishing process, for example. Inexamples where the portion of the substrate is etched, the etchingprocess may be mechanical, chemical and/or photochemical.

A portion of the fin containing defects (e.g., the defect region 211,the defect region 704) is removed (block 1104). For example, an etchprocess that only selectively etches the material of the fin and/or moreeffectively etches the material of the fin (as opposed to the substrate)is used. Additionally or alternatively, in some examples, an etchingsolution that etches the fin at a higher rate than substrate may beused.

In some examples, the fin is annealed (block 1106). In this example, thefin along with the overall die and/or wafer structure is hightemperature annealed at a temperature exceeding 450° C. In otherexamples, the die and/or wafer structure is low temperature annealed.

In some examples, an opening resulting from removing the defect portionof the fin (e.g., a cavity defined by etching the fin) is back filled(block 1108). In some examples, a non-conductive dielectric material isapplied to back fill the fin. In some examples, the fin is back filledto be relatively flush and/or aligned with a substrate surface (e.g., aback side of a substrate surface). Additionally or alternatively, theback fill material is polished and/or etched.

In some examples, the substrate and/or a portion of the fin with defectsis polished (block 1110) and the process ends. In particular, theportion of the fin and/or the substrate may be removed together in sucha polishing process. In some examples, a polishing process is used inlieu of an etching and/or selective etching process described above.

FIG. 12 is flowchart representative of another example method 1200 thatmay be used to implement the examples disclosed herein. In this example,a defect portion of a layered structure of a wafer and/or die is to beremoved to prevent potential leakage current issue(s). In this example,a defect portion is to be defined from dissimilar semiconductormaterials being applied, layered and/or coupled together (e.g., bydefining stacked multiple layers of dissimilar materials).

According to the illustrated example, a first semiconductor layer (e.g.,the substrate 706) is placed onto a second semiconductor layer (e.g.,the substrate 702), thereby defining a defect region (e.g., the defectregion 704) defined between the first and second semiconductor layers(block 1202). In particular, the lattice mismatch between the first andsecond semiconductor layers has caused the defect region to be defined.

In this example, the defect region is fully covered by the firstsemiconductor layer. In other words, in this example, the firstsemiconductor layer is not patterned onto the second semiconductorlayer, but instead applied as a layer (e.g., a covering layer). In otherexamples, the first semiconductor layer may be applied as a pattern(e.g., during a lithography process), thereby also defining a pattern ofthe defect region at an interface between the first and secondsemiconductor layers.

Next, metallization, additional layering and/or components are added(block 1204). In particular, the components such as transistors alongwith corresponding interconnects (e.g., metallic interconnects) may bedefined/added within and/or on the added first semiconductor layer.

The second semiconductor layer along with the defect region are removed(e.g., etched and/or polished) (block 1206) and the process ends. Forexample, a wafer on which a die is arranged in may be coupled to acarrier/fixture so that the second semiconductor layer along with thedefect region may be removed.

As described above, flowcharts representative of example methods forimplementing the examples disclosed herein are shown in FIGS. 11 and 12.The example methods may be implemented by machine readable instructionsthat comprise a program(s) for execution by a processor such as theprocessor 1312 shown in the example processor platform 1300 discussedbelow in connection with FIG. 13. The program, which may be implementedby semiconductor fabrication equipment, may be embodied in softwarestored on a tangible computer readable storage medium such as a CD-ROM,a floppy disk, a hard drive, a digital versatile disk (DVD), a Blu-raydisk, or a memory associated with the processor 1312, but the entireprogram and/or parts thereof could alternatively be executed by a deviceother than the processor 1312 and/or embodied in firmware or dedicatedhardware. Further, although the example program is described withreference to the flowcharts illustrated in FIGS. 11 and 12, many othermethods of implementing the examples disclosed herein may alternativelybe used. For example, the order of execution of the blocks may bechanged, and/or some of the blocks described may be changed, eliminated,or combined.

As mentioned above, the example methods of FIGS. 11 and 12 may beimplemented using coded instructions (e.g., computer and/or machinereadable instructions) stored on a tangible computer readable storagemedium such as a hard disk drive, a flash memory, a read-only memory(ROM), a compact disk (CD), a digital versatile disk (DVD), a cache, arandom-access memory (RAM) and/or any other storage device or storagedisk in which information is stored for any duration (e.g., for extendedtime periods, permanently, for brief instances, for temporarilybuffering, and/or for caching of the information). As used herein, theterm tangible computer readable storage medium is expressly defined toinclude any type of computer readable storage device and/or storage diskand to exclude propagating signals and to exclude transmission media. Asused herein, “tangible computer readable storage medium” and “tangiblemachine readable storage medium” are used interchangeably. Additionallyor alternatively, the example methods of FIGS. 11 and 12 may beimplemented using coded instructions (e.g., computer and/or machinereadable instructions) stored on a non-transitory computer and/ormachine readable medium such as a hard disk drive, a flash memory, aread-only memory, a compact disk, a digital versatile disk, a cache, arandom-access memory and/or any other storage device or storage disk inwhich information is stored for any duration (e.g., for extended timeperiods, permanently, for brief instances, for temporarily buffering,and/or for caching of the information). As used herein, the termnon-transitory computer readable medium is expressly defined to includeany type of computer readable storage device and/or storage disk and toexclude propagating signals and to exclude transmission media. As usedherein, when the phrase “at least” is used as the transition term in apreamble of a claim, it is open-ended in the same manner as the term“comprising” is open ended.

FIG. 13 is a block diagram of an example processor platform 1300 capableof executing the instructions of FIGS. 11 and 12 to implement theexamples disclosed herein. The processor platform 1300 can be, forexample, a semiconductor fabrication device, a wafer/die productioncontroller, a wafer producing/processing device, a die/wafer etchingdevice, a server, a personal computer, a mobile device (e.g., a cellphone, a smart phone, a tablet such as an iPad™), a personal digitalassistant (PDA), an Internet appliance, a set top box, or any other typeof computing device.

The processor platform 1300 of the illustrated example includes aprocessor 1312. The processor 1312 of the illustrated example ishardware. For example, the processor 1312 can be implemented by one ormore integrated circuits, logic circuits, microprocessors or controllersfrom any desired family or manufacturer.

The processor 1312 of the illustrated example includes a local memory1313 (e.g., a cache). The processor 1312 of the illustrated example isin communication with a main memory including a volatile memory 1314 anda non-volatile memory 1316 via a bus 1318. The volatile memory 1314 maybe implemented by Synchronous Dynamic Random Access Memory (SDRAM),Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory(RDRAM) and/or any other type of random access memory device. Thenon-volatile memory 1316 may be implemented by flash memory and/or anyother desired type of memory device. Access to the main memory 1314,1316 is controlled by a memory controller.

The processor platform 1300 of the illustrated example also includes aninterface circuit 1320. The interface circuit 1320 may be implemented byany type of interface standard, such as an Ethernet interface, auniversal serial bus (USB), and/or a PCI express interface.

In the illustrated example, one or more input devices 1322 are connectedto the interface circuit 1320. The input device(s) 1322 permit(s) a userto enter data and commands into the processor 1312. The input device(s)can be implemented by, for example, an audio sensor, a microphone, acamera (still or video), a keyboard, a button, a mouse, a touchscreen, atrack-pad, a trackball, isopoint and/or a voice recognition system.

One or more output devices 1324 are also connected to the interfacecircuit 720 of the illustrated example. The output devices 1324 can beimplemented, for example, by display devices (e.g., a light emittingdiode (LED), an organic light emitting diode (OLED), a liquid crystaldisplay, a cathode ray tube display (CRT), a touchscreen, a tactileoutput device, a printer and/or speakers). The interface circuit 1320 ofthe illustrated example, thus, typically includes a graphics drivercard, a graphics driver chip or a graphics driver processor.

The interface circuit 1320 of the illustrated example also includes acommunication device such as a transmitter, a receiver, a transceiver, amodem and/or network interface card to facilitate exchange of data withexternal machines (e.g., computing devices of any kind) via a network1326 (e.g., an Ethernet connection, a digital subscriber line (DSL), atelephone line, coaxial cable, a cellular telephone system, etc.).

The processor platform 1300 of the illustrated example also includes oneor more mass storage devices 1328 for storing software and/or data.Examples of such mass storage devices 1328 include floppy disk drives,hard drive disks, compact disk drives, Blu-ray disk drives, RAIDsystems, and digital versatile disk (DVD) drives.

The coded instructions 1332 of FIGS. 11 and 12 may be stored in the massstorage device 1328, in the volatile memory 1314, in the non-volatilememory 1316, and/or on a removable tangible computer readable storagemedium such as a CD or DVD.

Example 1 includes a multilayered die structure including a fin having afirst material, the fin epitaxially grown from a first substrate layerhaving a second material, where a defect portion of the fin is etched orpolished, and a second substrate layer having an opening through whichthe fin extends.

Example 2 includes the subject matter of Example 1, where the fin isannealed.

Example 3 includes the subject matter of any one of Examples 2 or 1,where the opening is back filled with gap material after the fin isselectively etched.

Example 4 includes the subject matter of any one of Examples 1-3, wherethe opening is polished to define a polished surface of the secondsubstrate layer.

Example 5 includes the subject matter of Example 4, and further includesa semiconductor layer above the polished surface.

Example 6 includes the subject matter of any one of Examples 1-5, andfurther includes a wire extending through the fin or along on an outersurface the fin.

Example 7 includes a processor including a plurality of transistors, aplurality of substrate layers, and a fin extending through at least oneof the plurality of substrate layers, where the fin is epitaxially grownfrom a substrate layer of the plurality of substrate layers that has adifferent material from the fin, and where a portion of the fin isetched or polished to reduce epitaxial defects at an interface betweenthe fin and the substrate layer.

Example 8 includes the subject matter of Example 7, and further includesgap fill material between an etched surface of the fin and the substratelayer.

Example 9 includes the subject matter of any one of Examples 7 or 8, andfurther includes an annealed surface proximate the fin.

Example 10 includes the subject matter of any one of Examples 7-9, andfurther includes a wire extending through the fin or along an outersurface the fin.

Example 11 includes a method of fabricating a multilayer die structureincluding removing at least a portion of a substrate semiconductormaterial to expose a defect region at an interface between the substratematerial and a deposited semiconductor material that is different fromthe substrate semiconductor material. The example method also includesremoving the exposed defect region.

Example 12 includes the subject matter of Example 11, where thedeposited semiconductor material includes a substrate layer.

Example 13 includes the subject matter of any one of Examples 11 or 12,where the deposited semiconductor material includes a fin that isepitaxially grown from the substrate semiconductor material.

Example 14 includes the subject matter of any one of Examples 11-13, andfurther includes annealing the die structure.

Example 15 includes the subject matter of any one of Examples 11-14, andfurther includes back filling an opening defined by etching or polishingthe exposed defect region.

Example 16 includes the subject matter of any one of Examples 11-15,where the opening is back filled with non-conductive gap fillermaterial.

Example 17 includes the subject matter of any one of Examples 11-16,where removing the exposed defect regions includes etching the exposeddefect region.

Example 18 includes the subject matter of Example 17, where etching theexposed defect occurs via at least one of a selective etching process ora timed chemical etch.

Example 19 includes a method including applying a first semiconductormaterial to a second semiconductor material that is different from thefirst semiconductor material to define a defect region therebetween, andremoving the exposed defect region.

Example 20 includes the subject matter of Example 19, and furtherincludes including etching or polishing at least one of the first orsecond semiconductor materials to expose the defect region.

Example 21 includes the subject matter of any one of Examples 19 or 20,where applying the first semiconductor material includes patterning thefirst semiconductor material onto the second semiconductor material.

Example 22 includes the subject matter of any one of Examples 19-21,where applying the first semiconductor material includes epitaxiallygrowing a fin from the second semiconductor material.

Example 23 includes the subject matter of any one of Examples 19-22, andfurther includes annealing the die structure.

Example 24 includes the subject matter of any one of Examples 19-23, andfurther includes back filling an opening that is defined by etching orpolishing the defect region.

Example 25 includes the subject matter of any one of Examples 19-24,where removing the defect region includes etching the defect region.

Example 26 includes the subject matter of Example 25, where etching thedefect region includes at least one of selective etching or a timedchemical etch.

From the foregoing, it will be appreciated that the above disclosedmethods, apparatus and articles of manufacture provide effective removalof defect regions resulting from epitaxial growth that can result inperformance degradation and/or negatively impact semiconductor deviceoperation.

Although certain example methods, apparatus and articles of manufacturehave been disclosed herein, the scope of coverage of this patent is notlimited thereto. On the contrary, this patent covers all methods,apparatus and articles of manufacture fairly falling within the scope ofthe claims of this patent. Although the examples disclosed herein havebeen shown in examples related to semiconductors and/or microprocessors,the examples disclosed herein may be applied to any other appropriateinterconnect (e.g., a layered interconnect) application(s) or etchingprocesses in general.

1. A multilayered die structure comprising: a fin having a firstmaterial, the fin epitaxially grown from a first substrate layer havinga second material, wherein a defect portion of the fin is etched orpolished; and a second substrate layer having an opening through whichthe fin extends.
 2. The multilayered die structure as defined in claim1, wherein the fin is annealed.
 3. The multilayered die structure asdefined in claim 1, wherein the opening is back-filled with gap materialafter the fin is selectively etched.
 4. The multilayered die structureas defined in claim 1, wherein the opening is polished to define apolished surface of the second substrate layer.
 5. The multilayered diestructure as defined in claim 4, further including a semiconductor layerabove the polished surface.
 6. The multilayered die structure as definedin claim 1, further including a wire extending through the fin or alongon an outer surface the fin.
 7. A processor comprising: a plurality oftransistors; a plurality of substrate layers; and a fin extendingthrough at least one of the plurality of substrate layers, the finepitaxially grown from a substrate layer of the plurality of substratelayers having a different material from the fin, wherein a portion ofthe fin is etched or polished to reduce epitaxial defects at aninterface between the fin and the substrate layer.
 8. The processor asdefined in claim 7, further including gap fill material between anetched surface of the fin and the substrate layer.
 9. The processor asdefined in claim 7, further including an annealed surface proximate thefin.
 10. The processor as defined in claim 7, further including a wireextending through the fin or along an outer surface of the fin.
 11. Amethod of fabricating a multilayer die structure comprising: removing atleast a portion of a substrate semiconductor material to expose a defectregion at an interface between the substrate material and a depositedsemiconductor material different from the substrate semiconductormaterial, wherein the deposited semiconductor material includes asubstrate layer; and removing the exposed defect region.
 12. (canceled)13. The method as defined in claim 11, further including a fin that isepitaxially grown from the substrate semiconductor material.
 14. Themethod as defined in claim 11, further including annealing the diestructure.
 15. The method as defined in claim 11, further including backfilling an opening defined by etching or polishing the exposed defectregion.
 16. The method as defined in claim 15, wherein the opening isback filled with non-conductive gap filler material.
 17. The method asdefined claim 11, wherein removing the exposed defect regions includesetching the exposed defect region.
 18. The method as defined in claim17, wherein etching the exposed defect occurs via at least one of aselective etching process or a timed chemical etch. 19.-26. (canceled)27. The method as defined in claim 11, further including applying thedeposited semiconductor material onto the substrate semiconductormaterial.
 28. The method as defined in claim 27, wherein applying thedeposited semiconductor material includes epitaxially growing a fin fromthe substrate semiconductor material.